Delta-Sigma analog to digital converters (ADCs) work by integrating (the Sigma) the difference (the Delta) between an input signal and an output value. The integrator is embedded in a feedback loop in such a way that the difference is driven to zero, making the output (a digital bit stream or word) equal in value to the input, which is a voltage or current. Hypothetically, for an ideal integrator, the delta would be precisely zero after settling. Typically, the integration is performed by an operational amplifier and a capacitor. Since the output is a digital value, it must be converted back to an electrical signal before it can be subtracted from the input to form the Delta. Usually, the output value is approximated by connecting a known reference to the input for some percentage of the time depending on the output bit stream. The average value of the reference multiplied by the duty cycle is driven to be equal to the input signal. The bit stream is then digitally filtered and down-sampled to produce the digital output word. Delta-sigma ADCs have a variety of uses, including in calibration equipment, meters, wireless communications audio equipment, and with imaging arrays.
One example of basic architecture for a delta-sigma ADC is provided in FIG. 1 (prior art). The ADC of FIG. 1 is a first order delta-sigma ADC and includes a count and dump decimator, and is not configured to take advantage of the unipolar input. Note that the switch allows the reference value to be sent either to the sum or to the difference port of the summing function, enabling the circuit of FIG. 1 to follow both positive and negative signal inputs. Some of the advantages of this design include having a 20-bit capable ADC, without a requirement for a secondary ADC. However, this design typically requires a large counter that must be present in each ADC. Further, for a given frame time, the maximum signal to noise ratio (SNR) is constrained by the pixel area, clock frequency, and power limitations.
There are two main reasons for using the type of ADC described above. First, a very precise delta-sigma ADC may be fabricated without using precision components. Second, a delta-sigma ADC can contain the signal within a limited bias range despite a large input dynamic range. One difficulty with prior art designs is that they generally employ an amplifier that consumes too much power for use in a large imaging array, such as an array of infrared detectors.
One attempt to improve the basic architecture is depicted in FIG. 2, which illustrates a “residue-readout” ADC (sometimes referred to as an “Eden” ADC) derived from a first order delta-sigma ADC. At the right of the drawing is a necessary auxiliary ADC. The main advantage of the ADC of FIG. 2 over a conventional one is the presence of a residue readout, which enables the use of a smaller counter for a given SNR requirement. The resolution of the over-all ADC can be set higher than permitted by the length of the counter because the residue information can be used to refine the digital output word. The auxiliary residue readout feature permits the residue-readout ADC to be operated as a delta-sigma ADC or a folding ADC. The residue-readout ADC takes advantage of the unipolar signal provided by image detectors by replacing the adding and subtracting of the reference seen in FIG. 1 with a single charge dump capacitor.
In the residue-readout ADC, the charge dump portion provides a constant delta-Q that provides for decrement of the integration capacitor by a known amount. The bottom of the dump capacitor may be connected to a special reference voltage, but ground can be used when layout constraints exist. As in all switched capacitor circuits, the switches provide a path for clock feed through, which appears as input offset current in the output digital word. Non-overlapping clock phases must be used. Further, noise is captured at the end of every charge dump event but auxiliary ADC quantization noise is the largest noise contribution.
While the residue-readout ADC does not require 20-bits in the cell (unlike conventional ADCs), it requires the noted auxiliary ADC and provides poor power per pixel when used in an imaging array. Sample and hold buffers are required for each pixel to provide the signal to the auxiliary ADC. Performance is limited by pixel array constraints, and implementation details. Often, the maximum signal to noise ratio (SNR) is constrained by residue read-out and the pixel area.
Ongoing research into focal plane arrays, such as infrared focal plane arrays (IR FPAs), has included embedded ADCs. Many implementations attempted have involved placement of an ADC on the column of the read-out integrated circuit (ROIC). At least one attempt has involved an effort to fit a high dynamic range ADC to every detector in an IR FPA. However, these implementations each require significant power to achieve the bandwidth for use in an imaging array. What is needed is a low power delta-sigma ADC, such as one that may be used in a large imaging array.